Since the discovery of graphene and realization of its exceptional electronic properties in suspended form, there have been many efforts in fabricating FET-type devices based on single and bilayer graphene on a SiO2 substrate. However, performance of these devices is found to be inferior to the expected intrinsic properties of graphene. It has been observed that apart from carrier mobility in graphene, which is sensitive to trapped charges, and surface impurities at the graphene-oxide interlace, breakdown current density in graphene depends sensitively on the heat dissipation property of the underlying supporting substrate. Although graphene has extremely high intrinsic thermal conductivity, it is reported that in graphene devices that more than 70% of the heat dissipates through the 300 nm SiO2 on silicon directly below the active graphene channel. The remainder of the heat is carried to the graphene that extends beyond the device and metallic contacts. Such a distribution of heat into the substrate cause undesirable effects on the overall performance of a device, such as the thermally generated carriers affecting the electronic mobility parameters of a device fabricated on top of the substrate.
The breakdown current density measurements of multilayer and few layer graphene disposed on a SiO2/Si substrate have been reported to be in the range of 7×107 to 108 A/cm2. The main breakdown mechanism of graphene is mostly due to the Joule heating, which sensitively depends upon the thermal conductivity and surface roughness of the underlying substrate. The thermal conductivity of SiO2 K=0.5-1.4 W/mK at RT is more than two orders-of-magnitude smaller than that of Si, K=145 W/mK, which suggests that the use of a better heat-conducting material, directly below graphene, can improve graphene's JBR. Recently, it was demonstrated that replacement of SiO2 with diamond-like carbon (DLC) helps to substantially improve the RF characteristics of the scaled graphene transistors. However, DLC is an amorphous material with K=0.2-3.5 W/mK at room temperature (hereinafter “RT”), which is a very low value and is close to that in SiO2. Additionally, depending on the hydrogen content, the as deposited DLC films has high internal stress, which needs to be released by having to perform a separate step of annealing these films at higher temperatures (about 600° C.). These negative attributes provide a very strong motivation for the search for other materials which can be used as substrates for graphene based devices.